A CMOS imager circuit includes a focal plane array of pixel cells, each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion node, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion region. The imager may also include a transistor for transferring charge from the photosensor to the floating diffusion node and another transistor for resetting the floating diffusion region node to a predetermined charge level prior to charge transference. Each pixel cell is isolated from other pixel cells in the array by a field oxide region (STI), which surrounds it and separates the doped regions of the substrate within that pixel cell from the doped regions of the substrate within neighboring pixel cells.
In a CMOS imager, the active elements of a pixel cell, for example a four transistor pixel, perform the necessary functions of (1) photon to charge conversion; (2) transfer of charge to the floating diffusion node; (3) resetting the floating diffusion node to a known state before the transfer of charge to it; (4) selection of a pixel cell for readout; and (5) output and amplification of a signal representing a reset voltage and a pixel signal voltage based on the photo converted charges. The charge at the floating diffusion node is converted to a pixel output voltage by a source follower output transistor.
FIG. 1 illustrates a block diagram of a CMOS imager device 100 having a pixel array 110 with each pixel cell being constructed as described above. Pixel array 110 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 110 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 110. The row lines are selectively activated by the row driver 145 in response to row address decoder 155 and the column select lines are selectively activated by the column driver 160 in response to column address decoder 170. Thus, a row and column address is provided for each pixel.
The CMOS imager is operated by a control circuit 150, which controls decoders 155, 170 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 145, 160, which apply driving voltage to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal Vrst and a pixel image signal Vsig for each pixel are read by sample and hold circuitry 161, 162 associated with the column device 160. A differential signal Vrst-Vsig is produced for each pixel, which is amplified and digitized by analog-to-digital converter 175. The analog to digital converter 175 converts the analog pixel signals to digital signals which, are fed to an image processor 180 to form a digital image.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524, and 6,333,205, assigned to Micron Technology, Inc. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
A schematic diagram of an exemplary CMOS four-transistor (4T) pixel cell 10 is illustrated in FIG. 2. The four transistors include a reset transistor 34, source follower transistor 36, row select transistor 38 and a transfer gate 32. A photosensor 40 converts incident light into an electrical charge. A floating diffusion region 50 receives the charge from the photosensor 40 through the transfer gate 32 (when activated by a transfer gate control signal TG) and is connected to the reset transistor 34 and the gate of the source follower transistor 36. The source follower transistor 36 outputs a signal proportional to the charge accumulated in the floating diffusion region 50 when the row select transistor 38 is turned on. The reset transistor 34 resets the floating diffusion region 50 (when activated by a reset control signal RST) to a known potential prior to transfer of charge from the photosensor 40. The photosensor 40 may be a photodiode, photogate, or photoconductor. If a photodiode is employed, the photodiode may be formed below a surface of the substrate and may be a buried PNP photodiode, buried NPN photodiode, a buried PN photodiode, or a buried NP photodiode, among others.
In a conventional CMOS imager pixel with a buried photodiode, the photodiode converts incident light to an electrical charge. The photodiode accumulates this charge throughout the sampling period. At the end of the sampling period, the transfer gate closes (i.e., is activated) and the charge is drained from the photodiode through the transfer gate.
A buried photodiode has a shallow implant of a first conductivity (referred to herein as an accumulation region) above a deeper implant of another conductivity (referred to herein as a charge-collection region) in a substrate lightly doped with the first conductivity type. A depletion region exists at the interface between the accumulation region and the charge collection region. For example, in a p-type substrate, a shallow low-dose p-type implant is applied over an n-type photosensitive region. This also produces a dual-junction sandwich that alters the visible light spectral response (the sensitivity to optical radiation of different wavelengths) of the pixel. The upper junction is optimized for responding to lower wavelengths while the lower junction is more sensitive to the longer wavelengths.
However, the top surface of the photodiode is electrically connected to the bulk substrate via a portion of the accumulation region above the charge-collection region and a portion of the accumulation region between the field oxide region (referred to hereinafter as a STI region) and the charge-collection region. The depletion of charge from the substrate and accumulation region causes excessive leakage and creates a false signal, commonly known as “dark current.” Dark current is a current that is created without photoconversion of light. Dark current may be reduced by preventing depletion of the accumulation region.
Attempts to overcome a depletion of the accumulation region have involved increasing the doping level near the STI sidewall. However, increasing the doping level near the STI sidewall creates excess leakage, which is quite significant in the overall dark current leakage level in a pinned photodiode.
Therefore, it is desirable to create an isolation structure where pinned photodiode characteristics are maintained without increased doping levels.